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NIS3001 Integrated Driver and MOSFET Power Chip for Synchronous Buck Controllers
The NIS3001 is an integrated multi-chip solution for high power DC to DC synchronous buck converters. It contains two power MOSFETs that are controlled by an internal Driver. All three die are packaged in a power QFN package called PInPAKTM. The 10.5 by 10.5 mm PInPAKTM package increases power density and simplifies PCB layout. The device can be used in single or multi-phase applications. The NIS3001 implements the newest MOSFET technology. The control MOSFET is designed to provide improved switching performance and operates at a much lower temperature compared to discrete solutions. The synchronous MOSFET is designed to reduce conduction and switching losses at high frequencies. The integrated solution greatly reduces the parasitic inductance associated with conventional discrete buck converters and results in the highest power conversion efficiency. The power density of the NIS3001 is optimized based on MOSFET die size and PInPAK design. The PInPAK layout allows for direct routing into each power terminal. This results in a better thermal solution for the system. In addition its thermal resistance is 50% lower than BGAs. In summary, the NIS3001 has an improved efficiency, reliability and scalability for multi-phase synchronous buck converters.
Features http://onsemi.com MARKING DIAGRAM
CASE 500 PInPAK 10.5x10.5 PLLP
NIS3001QP AWLYYWW
NIS3001 = Specific Device Code A = Assembly Site WL = Wafer Lot YY = Year WW = Work Week
PINOUT DIAGRAM
14 15 16 17 11 12 13 18 19 20 10 7 5 9 8 21 1 2 3 4
* * * * * * * *
Matched MOSFETs for Optimal Efficiency 10.5 mm x 10.5 mm Power QFN Package, PInPAK 25 A DC Output Current 7.0 to 14 V Input Voltage Range Internal Thermal Shutdown Operating Frequency Range up to 1,000 kHz 0.7 V to 5.1 V Output Voltage Range Nominal Duty-Cycle 5% to 50%
Hi Side Discrete FETs Lo Side Discrete FETs
6
(Bottom View)
ORDERING INFORMATION
Device NIS3001QPT1 Package PInPAK Shipping 1500/T ape & Reel
VIN
VS
Analog Driver IC
DRN
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
PGND
Figure 1.
(c) Semiconductor Components Industries, LLC, 2003
1
October, 2003 - Rev. 5
Publication Order Number: NIS3001/D
NIS3001
BST (17) TG (15, 16) VIN (12, 13)
(4) VS + - + - 4.35 V Delay
Level Shifter
EN
Delay Thermal Shutdown VS
(1) CO (2, 19) GND
Figure 2. Block Diagram
PIN FUNCTION DESCRIPTIONS
Pad # 1 2, 19 3 4 5, 6 7-11, 14, 18 12, 13 15, 16 17 20, 21 Symbol CO GND EN VS PGND DRN Description Logic level control input produces complementary output states. Signal ground. Logic level enable input forces internal driver top gate and bottom gate low, and supply current to less than 10 mA when EN is low. Power supplied to the internal driver. A 1.0 mF ceramic capacitor should be connected from this pin to PGND. Power ground. High current return path for the lower internal. Switching Node, connected to output inductor (10). Switching Node, connected to the boost capacitor (14). All pins connected internally. DC-DC converter input voltage. High Side Driver Output (Top Gate, this pin is used to monitor the gate). Bootstrap supply voltage input. In conjunction with a Schottky diode to Vs, a 0.1 mF to 1.0 mF ceramic capacitor connected between BST and DRN (14). Low Side Driver Output (Bottom Gate, this pin is used to monitor the gate).
VIN TG BST BG
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2
+ -
(3)
Non-Overlap Control
4.0 V
DRN (7-11, 14, 18)
BG (20, 21)
PGND (5, 6)
NIS3001
MAXIMUM RATINGS*
Rating Operating Junction Temperature, TJ Output DC Current Package Thermal Resistance: Junction to Ambient, RqJ-A (4 layer PCB with vias, no air flow) Junction to Ambient, RqJ-A (4 layer PCB with vias, 200lfm air flow) Junction to PCB, RqJ-PCB (4 layer PCB with vias) Storage Temperature Range, TS ESD Susceptibility (Human Body Model) Lead Temperature Soldering: JEDEC Moisture Sensitivity Level Pin Symbol VS Pin Name Driver Supply Voltage MAX 6.3 V MIN -0.3 V ISOURCE NA Reflow: (SMD styles only) (Note 1) Value 125 25 26 13 8.0 -65 to 150 500 230 peak 3 ISINK 4.0 A Peak (< 100 ms) 250 mA DC 4.0 A Peak (< 100 ms) 250 mA DC NA C V C MSL Unit C A C/W
BST
Bootstrap Supply Voltage Input Switching Node (Bootstrap Supply Return)
25 V wrt/PGND 6.3 V wrt/DRN 25 V
-0.3 V wrt/DRN
NA 4.0 A Peak (< 100 ms) 250 mA DC 4.0 A Peak (< 100 ms) 250 mA DC 4.0 A Peak (< 100 ms) 250 mA DC 1.0 mA 1.0 mA 4.0 A Peak (< 100 ms) 250 mA DC -
DRN
-1.0 V DC -5.0 V for 20 ns -6.0 V for 20 ns -0.3 V wrt/DRN
TG
High Side Driver Output (Top Gate) Low Side Driver Output (Bottom Gate) TG & BG Control Input Enable Input Ground
25 V wrt/PGND 6.3 V wrt/DRN 6.3 V
4.0 A Peak (< 100 ms) 250 mA DC 4.0 A Peak (< 100 ms) 250 mA DC 1.0 mA 1.0 mA NA
BG
-0.3 V
CO EN PGND
6.3 V 6.3 V 0V
-0.3 V -0.3 V 0V
VIN
Input Supply Voltage
14 V
-
-
NOTE: All voltages are with respect to PGND except where noted. 1. 60 seconds maximum above 183C. *The maximum package power dissipation must be observed.
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NIS3001
ELECTRICAL CHARACTERISTICS
(Test conditions unless otherwise noted; VIN = 12 V, VS = VBST = VEN = 5 V, FSW = 500 kHz, VCO = 4 V) Characteristic DC OPERATING SPECIFICATIONS Power Supply Power Loss VOUT = 1.5 V, IOUT = 4.5 A VOUT = 1.5 V, IOUT = 15 A VS Operating Current (switching) VS Quiescent Current, Shutdown, VEN = 0 V Bootstrap Operating Current (switching) EN Input Characteristics Enable Input Bias Current EN High Threshold, (Operating), VIN = open EN Low Threshold, (Shutdown), VIN = open Undervoltage Lockout Undervoltage Lockout, Turn on, (VCO = VEN = 4 V, VIN = open) Undervoltage Lockout, Turn off, (VCO = VEN = 4 V, VIN = open) Hysteresis for Undervoltage Lockout, (VCO = VEN = 4 V, VIN = open) CO Input Characteristics CO Input Bias Current, (VIN = open, VCO = 4 v) CO High Threshold, VIN = open CO Low Threshold, VIN = open Thermal Shutdown Overtemperature Trip Point Hysteresis AC OPERATING SPECIFICATIONS High-Side Driver Propagation Delay Time, TG Going High (Nonoverlap time); 50% between BG (going low) and TG (going high) VBST - VDRN = 5.0 V Propagation Delay Time, TG Going Low; 50% between CO (going low) and TG (going low) VBST - VDRN = 5.0 V Propagation Delay Time, BG Going High (Nonoverlap time); 50% between DRN (going low) and BG (going high) Propagation Delay Time, BG Going Low; 50% between CO (going high) and BG (going low) POWER MOSFET ON CHARACTERISTICS High-Side Driver Static Drain-to-Source On-Resistance (VGS = 5 V, ID = 20 A) Low-Side Driver Static Drain-to-Source On-Resistance (VGS = 5 V, ID = 20 A) RDS(on) - 3.19 - mW RDS(on) - 10.5 - mW tpdhTG tpdlTG tpdhBG tpdlBG - - - - 45 60 43 8.0 - - - - ns ns ns ns - - 170 30 - - C C ICO VCO VCO - 2.0 - 3 - - - - 0.8 nA V V UVLO UVLO Vhyst 4.0 3.7 - 4.25 4.0 275 4.48 4.3 - V V mV IEN VEN VEN - 2.0 - 1 - - - - 0.8 mA V V PLOSS - - IVS IVS IBST - - - 0.85 2.67 19 10 7 - - - - 10 mA mA mA W Symbol Min Typ Max Unit
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NIS3001
PIN = (VVS * IVS) + (VIN * IIN) POUT = (VOUT * IOUT) Efficiency = POUT/PIN PLOSS = PIN - POUT BST Average VS Voltage 5V + A V EN Driver DRN Average - VS Current VS Average Output Current A Load CO GND BG PGND Averaging Circuit Average V Output Voltage TG VIN Average Input Voltage V Average Input Current A + - 12 V
PWM Signal
This Test Circuit was used to characterize the NIS3001 during operation.
Figure 3. Test Circuit
TYPICAL PERFORMANCE CURVES
9 8 PLOSS, POWER LOSS (W) 7 6 5 4 3 2 1 0 0 5 10 15 20 25 IOUT, OUTPUT CURRENT (A) TA = 25C VIN = 12 V VVS = 5.0 V VOUT = 1.5 V Airflow = 200 lfm FSW = 1000 kHz 750 kHz 500 kHz 350 kHz h, EFFICIENCY (%) 96 94 92 90 88 86 750 kHz 84 FSW = 1000 kHz 82 80 0 5 10 15 20 25 IOUT, OUTPUT CURRENT (A) 350 kHz 500 kHz TA = 25C VIN = 12 V VVS = 5.0 V VOUT = 1.5 V Airflow = 200 lfm
Figure 4. Power Loss versus Output Current
25 IVS, DRIVER CURRENT (mA) IVS, DRIVER CURRENT (mA) TA = 25C 23 40 35 30 25 20 15 10 5 0 4.5 5 5.5 6
Figure 5. Efficiency versus Output Current
TA = 25C
21
19
17 15
VIN = 12 V VEN = 3.5 V FSW = 500 kHz VOUT = 1.5 V IOUT = 15 A
VIN = 12 V VVS = 5.0 V VEN = 3.5 V VOUT = 1.5 V IOUT = 15 A 100 200 300 400 500 600 700 800 900 1000
VVS, DRIVER VOLTAGE (V)
FSW, SWITCHING FREQUENCY (kHz)
Figure 6. Driver Current versus Driver Voltage
Figure 7. Driver Current versus Switching Frequency
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NIS3001
30 IOUT, OUTPUT CURRENT (A) PLOSS, POWER LOSS (W) 25 20 15 10 5 0 25 50 75 100 125 TPCB, TEMPERATURE PCB (C) 2.3 4.5 5.0 5.5 6.0 VVS, DRIVER VOLTAGE (V) 2.7 TA = 25C VIN = 12.0 V VOUT = 1.5 V IOUT = 15 A FSW = 500 kHz Airflow = 200 lfm
2.6
2.5
2.4
Figure 8. Safe Operating Area; Output Current versus Temperature PCB
96 FSW = 500 kHz 94 h, EFFICIENCY (%) PLOSS, POWER LOSS (W) 3.5 4.0
Figure 9. Power Loss versus Driver Voltage
FSW = 500 kHz
92
3.0 TA = 25C VIN = 12 V IOUT = 15 A VVS = 5.0 V Airflow = 200 Ifm 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
90
88 86 1.0 1.5 2.0 2.5 3.0 3.5
TA = 25C VIN = 12 V IOUT = 15 A VVS = 5.0 V Airflow = 200 Ifm 4.0 4.5 5.0
2.5
2.0 VOUT, OUTPUT VOLTAGE (V) VOUT, OUTPUT VOLTAGE (V)
Figure 10. Efficiency versus Output Voltage
Figure 11. Power Loss versus Output Voltage
98 96 h, EFFICIENCY (%) 94 92 90 88 86 84 82 80 5.0 10 15 20 25 IOUT, OUTPUT CURRENT (A) TA = 25C VIN = 12 V FSW = 500 kHz VVS = 5.0 V Airflow = 200 lfm 2.2 V 1.5 V VOUT = 1.0 V 5.0 V 3.0 V 4.0 V
Figure 12. Efficiency versus Output Current at Different Output Voltages
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NIS3001
1.75 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) VGS = 5 V ID = 20 A RDS(on) = 10.5 mW 1.75 VGS = 5 V ID = 20 A RDS(on) = 3.19 mW
1.50
1.50
1.25
1.25
1.00
1.00
0.75 0.50 -50
0.75 0.50 -50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 13. Top MOSFET On-Resistance Variation with Temperature
Figure 14. Bottom MOSFET On-Resistance Variation with Temperature
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NIS3001
INTRODUCTION The NIS3001 represents a significant improvement in high frequency power conversion, by combining a high performance driver with two power MOSFET devices for use in synchronous buck converters. All three die are assembled in a QFN package called a PInPAK. This approach minimizes the parasitic elements in the power path by reducing the distance between the three devices. The leadless design also provides an excellent thermal path for the removal of heat which is generated during the power conversion process. All of these improvements result in a higher conversion efficiency when operation at high frequencies (350 kHz to 1000 kHz) is required. Operating at higher frequencies, reduces the number of electrolytic capacitors and the size of filter inductors required to meet load line and transient response requirements. This device is designed to process power from a nominal 12 V source (ranging from 7 V to 14 V), while obtaining its internal bias power from a 5 V supply. The output voltage can range from 0.7 V to 5.1 V with a maximum duty cycle of 50%. It requires signal inputs from a synchronous buck controller, such as the NCP5316. A minimum number of external components are required to create a complete power converter. Figure 15 is an example of a simplified solution. Operational Description Driver: The internal driver requires a nominal 5 volt bias voltage to operate. The bootstrap voltage is normally derived from this same source. The bootstrap circuit typically employs a schottky diode as part of the charge pump that provides the isolated supply voltage to the high side driver. The driver uses several control functions to provide the correct gate drive signals. The control (CO) input accepts the drive signal from the synchronous converter PWM. The driver circuitry programs a delay between the top and bottom FETs, such that they will not conduct at the same time. An enable pin (EN) allows the output of the driver to be shut down by a logic level signal. In this mode of operation, the bias current is reduced to a level of 10 mA. When the driver is disabled, the gates of both FETs are low and the drain (DRN) output of the NIS3001 is in a high impedance state. To guarantee system integrity, the driver also incorporates an internal UVLO circuit. It is activated when the bias voltage reaches 4.25 volts, and will shut down the driver when if the bias voltage drops below 3.975 volts. In the UVLO shutdown condition, both FETs are off, and the DRN pin is in a high impedance state. Power MOSFETs: The NIS3001 contains two power FETs which are directly connected to the internal driver chip. They have different on resistances and are designed for optimum performance for current VRM voltage and current requirements. The drain of the top FET is connected to the 12 volt input and the source is connected to the DRN pins. The drain of the bottom FET is also connected to the DRN pins, while its source is connected to the power ground pins. Functional Pin Description VS Pin: The VS pin connects to a nominal 5 volt supply and provides power to the driver chip. It is necessary to provide a bypass capacitor between 1.0 mF and 10.0 mF in close proximity to this pin and the ground (GND) pin. This capacitor allows a low impedance path for the high frequency currents that occur when the gate of the bottom FET switches. The voltage at this pin is monitored internally by the UVLO circuit which will disable the driver if there is not sufficient voltage available to assure proper operation of the driver. VIN Pin: The VIN pin connects to the nominal 12 volt supply which provides power to the switching stage of the converter. It connects to the drain of the top FET, which is the controlled switch of the buck converter. This pin needs a combination of electrolytic and ceramic capacitors for bypass purposes. Enable Pin: The EN pin accepts a logic level signal that can both source and sink current. There is no hysteresis on the signal switching levels for this pin, so care should be taken that the high and low logic levels of the driving signal should be above and below the switching points by several hundred millivolts. In its high state, the driver is operational and will respond to inputs on the CO pin. In its low state, the driver is disabled. In this state, it enters a reduced power mode and turns off both FETs, thereby providing a high impedance output at the DRN pin. A bypass capacitor is not normally required for the enable signal. Control Pin: The CO pin accepts a logic signal from the PWM output of the controller chip. This signal is fed into the driver and controls the top and bottom FETs. When this pin is in a high state, the top FET is fully enhanced and the bottom FET is not conducting. When the signal is low, the bottom FET is fully enhanced and the top FET is not conducting. During the switching transition, there is a non-overlap control circuit that is designed to provide optimum switching timing for the two FETs. This circuit eliminates the possibility of cross conduction, by monitoring the voltage on the DRN pin to time the turn-on of the bottom FET. Bootstrap Pin: The BST pin connects to an external diode-capacitor circuit that acts as a charge pump to provide a floating, isolated voltage source for the high-side driver. A schottky diode is recommended, which charges the capacitor when the DRN pin is low. This diode is normally connected to the same source as the VS pin. The capacitor (typically 0.2 to 1.0 mF) is connected from the BST to the DRN pin. The capacitor should be mounted as close as possible to the NIS3001 package. As there are
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NIS3001
several DRN pins available, it is recommended that pin 14 be used because of its proximity to the BST pin. Drain Pin: The DRN pin is also called the switch node. It is the connection between the source of the top FET and the drain of the bottom FET. This node is connected to one terminal of the output filter inductor. When the top FET is conducting, the DRN pin is essentially connected to the 12 volt source. When the bottom FET is conducting, this node is essentially connected to ground. When the driver is disabled, this node is in a high impedance state, and is essentially connected to neither. Top Gate Pin: The TG pin is the internal connection of the output of the high-side driver and also the gate of the top FET. There is normally no connection to this pin. It can however, be used to drive an external FET which will operate in parallel with the top FET. This pin may also be attached to the pcb for additional heat sinking or used to monitor the top gate waveform. Bottom Gate Pin: The BG pin is the internal connection of the output of the lower driver and bottom FET gate. There is normally no connection to this pin, although it may be used for paralleling an additional FET, monitoring or heat sinking, similar to the TG pin. Power Ground: The PGND pin is the power ground for the device. The source of the bottom FET is also connected to this pin. This pin is not internally connected to the GND pin and care should be taken when laying out the circuit to maintain proper isolation between these grounds. Signal Ground: The GND pin is the ground pin for the driver, and is internally isolated from the PGND pin. Layout Considerations While the design of the NIS3001 reduces many of the parasitic elements when compared to a discrete solution, careful consideration to layout must still be observed. The following suggestions are offered: a) Mount the bootstrap capacitor very close to the package. Use DRN pin 14 and BST pin 17 due to their proximity. The capacitor should be a high quality ceramic type. Mount the VS pin bypass capacitor as close as possible to the package. This should be a high quality ceramic capacitor and is mounted between pins 4 and 2. VIN requires a combination of bypass capacitors. These consist of both low ESR aluminum electrolytics and high quality ceramics. The ceramics should be SMT devices and mounted as close to the VIN and PGND pins as possible. The aluminum capacitors are generally located slightly farther away, but should be connected via power and ground planes to maintain the lowest possible impedance. The total amount of capacitance required is dependant on the system requirements. Keep as much copper area as possible on all layers in the proximity of the device for best thermal performance. Especially, keep large copper areas connected to the large pads on the chip, and use thermal vias to transmit the heat to the bottom side of the board when possible. All vias underneath the chip, whether thermal or not should be plugged with epoxy or some material other than solder. The amount of solder paste used for mounting is important to a good connection. Empty vias can siphon off solder during the mounting process and leave voids, while soldered vias may contribute solder and cause shorts below the chip. Power and ground (PGND) busses should be distributed through power and ground planes. These should feed through vias to the appropriate pads for the 12 volts, switch node and ground connections. The impedances of the high current paths are critical for optimum efficiency.
b)
c)
d)
e)
f)
+ - BST VS 5V + - EN DRIVER DRN RL CO GND BG PGND VOUT TG VIN 12 V
Figure 15.
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C4A1
C3A3
C2A2
C1A2
LSCI 12 V Filter
ATX 12 V
12 V Filter
R8*
5V
{R61*
R1 C1 C2 R2 R3 D42 C47 R45 R4* R5* C3 R21 R7 C49 C50 C48 48 47 46 45 44 43 42 41 40 39 38 37 R6* 17 7-11 12, 13 14, 18 R17 L2 R44 C7
R60*
R59*
C11*
Q41*
D47*
VCCP
R46
R26
R24
R28
VCC3 VCCL VREF IO IOF ILIM VDRP IPLIM CS3N CS3P CS2N CS2P CS1N
C6
20, 21 15, 16 BG TG 1 CO BST 2 GND DRN 3 NIS3001 EN VIN 4 VS DRN PGND C46 5, 6
R25
R27
R29
R50 D44 C57 17 7-11 12, 13 14, 18 C59 C60 C58 R19 L4 C9
VID5 JIF5.2 JIF4.2 JIF3.2 JIF2.2 JIF1.2
NCP5316
R51
NIS3001
R8802*
SSTART
R16 C4 C5 R54 D45
13 14 15 16 17 18 19 20 21 22 23 24
DRVON SS ENABLE VFFB VFB COMP NC NC CS6N CS6P CS5N CS5P
Figure 16. Application Diagram, Three-Phase Converter
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R9 R15 R10
10
NTC R12 Thermistor near closest R13 inductor
R8801* R501*
VOUT
R52
VSS_DIE PWRGD
R502*
1 2 3 4 5 6 7 8 9 10 11 12
VID5 VID0 VID1 VID2 VID3 VID4 LGND NC NC SGND PWRGD PWRLS
20, 21 15, 16 BG TG 1 CO BST 2 DRN GND 3 NIS3001 EN VIN 4 VS DRN PGND C56 5, 6
CS1P ROSC VCC GATE1 GATE2 GATE3 GATE4 GATE5 GATE6 GND CS4P CS4N
36 35 34 33 32 31 30 29 28 27 26 25
Item 3 Qty. 40 Item 2 Qty. 10 GND
R30
GND
R53 C62 17 7-11 12, 13 14, 18 C64 C65 C63 R20 L5 C10
SGND near socket VFFB connection
ENABLE
R55
TP2
ENABLE TPOINT
20, 21 15, 16 BG TG 1 CO BST 2 GND DRN 3 NIS3001 EN VIN 4 VS DRN PGND C61 5, 6
R22
GND
R11
AGND_A
* Optional { If 5 V from silver box this resistor is used, { otherwise it is removed
Connects GND and AGND_A
CPU_VCC_SENSE
NIS3001
3 Phase Voltage Regulator (VRD) Recommended Bill of Materials
Item 1 2 Quantity 10 10 Reference C1,C2,C3,C4,C5,C6,C7, C9,C10 C1B5,C1B6,C1B7,C2B12 C2B13,C2B14, C2B15,C3B9,C3B10, C3B11 3 40 C2D1,C2C1,C2D2,C2C2, C2D3,C2C3, C2D4,C2C4,C2D5,C2C5, C2D6,C2C6, C2D7,C2C7,C2D8,C2C8, C2D9,C2C9, C2D10,C2C10,C2D11, C2C11,C2D12, C2C12,C2C13,C2C14, C2C15,C2C16, C2C17,C2C18,C2C19, C2C20,C2C21, C2C22,C2C23,C2C24, C2C25,C2C26, C2C27,C2C28 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 6 6 3 4 3 3 1 2 2 1 1 1 1 1 1 1 2 3 1 7 6 C46,C47,C56,C57,C61, C62 C49,C50,C59,C60,C64, C65 C48,C58,C63 C4A1,C3A3,C2A2,C1A2 D42,D44,D45 L2,L4,L5 L5C1 R2,R1 R3,R7 R9 R10 R11 R12 R13 R22 R15 R16,R61 R17,R19,R20 R21 R24,R25,R26,R27,R28, R29,R30 R44,R45,R50,R51,R53, R54, 1mF 10mF 10nF 1800mF Schottky 280nH 275nH 6.65K 10 _ 2.10K 15K 20 K 2.00 K 15K@ T=25C 0_ 1K 0_ 18.2K 63.4K 1.5K 2.2_ SM C0805 SM C1210 SMC0603 23X10 mm/5.5 mm SOT-23 18.0 x 8.12 10.16 x 8.12 R0805 R0805 R0805 R0805 R0805 R0805 R0805 R0805 R0805 R0805 R0805 R0805 R0805 R0805 16V 16V 16V 16V 30V/ 0.2A 30Adc 16Adc "1%, 1/8 W" "10%, 1/8W" "1 %, 1/8W" "10%, 1/8W" "10%, 1/8W" "10%, 1/8W" 200mW "10%, 1/8W" "10%, 1/8 W" "10%, 1/8W" "1%, 1/8 W" "1%, 1/8 W" "10%, 1/8W" "10%, 1/8W" muRata muRata muRata Rubycon ON Semiconductor Coiltronics, Incorporated Coiltronics, Incorporated VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY muRata NTC Thermistor VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY CTX15-14771 CRCW08056651FRT1 CRCW0805100JT1 CRCW08052101FRT1 CRCW0805153JT1 CRCW0805203JT1 CRCW0805202JT1 NCP21XW153J03RA CRCW0805R00JT1 CRCW0805102JT1 CRCW0805R00JT1 CRCW08051822FT1 CRCW08056342FT1 CRCW0805152JT1 CRCW08052R2JT1 TDK NTCG203NH153JT GRM21B71C105KA01L GRM31CR61C106KC31L GRM188R71H103KA01L 16 MBZ 1800 M 10X23 BAT54LT1 TDK TDK TDK C2012X7R1C105K C3225X7R1C106KT C1608X7R1H103K 10mF Value 10nF 560mF Size SM C0603 Size E, 8 x 10.5mm 3.5mm, 0.60mm SM 1206 6.3V Rating 50V 4V Vendor muRata SANYO OS-CON SEPC Series muRata Part Number GRM188R71H103KA01L 4SEPC560M(E13) ;+/-20% (M) GRM31CR70J106KA01L TDK C3216X5R0J106M Vendor TDK Part Number C1608X7R1H103K
R61 is used to connect the NIS3001 Vs pin to 5V supply only. If different voltage is required items 29 thru 33 are needed.
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NIS3001
3 Phase Voltage Regulator (VRD) Recommended Bill of Materials
Item 25 26 27 Quantity 3 1 1 Reference R46,R52,R55 U1 PCB Value 2.2_ 4/5/6 Phase IC 4 layer 1 oz cCu ea Integrated Module Size SMR0603 LQFP-48 9 X 9 mm 6.3 x 6.0 inches FR4 Rating "10%, 1/10W" Vendor VISHAY ON Semiconductor CGI Circuits Part Number CRCW06032R2JT1 NCP5316 ONS 7 Rev C Vendor Part Number
28
3
U42, U44, U45
10.5 X 10.5 mm
25 Arms
ON Semiconductor
NIS3001
OPTIONAL PARTS
29 30 31 32 1 1 1 1 C11 R59 R60 Q41 10nF 1K 2.2_ NPN Bipolar X-sistor Zener Regulator N/A N/A N/A SM C0603 R0805 R0805 SOT-223 50V "10%, 1/8W" "10%, 1/8W" 30V/ 3A 0.225W/ 6.8 V muRata VISHAY VISHAY ON Semiconductor GRM188R71H103KA01L CRCW0805102JT1 CRCW08052R2JT1 MMJT9410T1
33 34 35 36
1 2 2 4
D47 R8801, R8802 R501, R502 R4, R5, R6, R8
SOT-23
ON Semiconductor
BZX84C6V8LT1
R61 is used to connect the NIS3001 Vs pin to 5V supply only. If different voltage is required items 29 thru 33 are needed.
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NIS3001
APPLICATION INFORMATION INTRODUCTION Various ON Semiconductor components are packaged in an advanced Quad Flat-pack No-Lead Package (QFN) or commonly referred to as a Leadless Package. Because the QFN(Leadless) platform represent the latest in surface mount packaging technology, it is important that the design of the Printed Circuit Board (PCB), as well as the assembly process, follow the suggested guidelines outlined in this document.
NIS3001 Package Overview
The QFN platform offers a versatility, which allows either a single or multiple semiconductor devices to be connected together within a leadless package. In this case the NIS3001 Package contains multiple semiconductor devices within one package. This package style was chosen due to its excellent thermal dissipation and reduced electrical parasitics. When surface mounting this package onto a PCB, two critical issues must be considered: 1. Printed Circuit Board Design 2. Board Mounting Process. This document will address both of these critical issues. Printed Circuit Board Design Considerations
SMD and NSMD pad configurations
Typically, the NSMD pads are preferred over the SMD configuration since defining the location and size of the copper pad is easier to control than the solder mask. This is based on the fact that the copper etching process is capable of a tighter tolerance than the solder masking process. In addition, the SMD pads will inherently create a stress concentration point where the solder wets to the pad on top of the lead. This stress concentration point is eliminated when the solder is allowed to flow down the sides of the leads in the NSMD configuration.
NSMD Pad Configurations
There are two different types of PCB pad configurations commonly used for surface mount leadless QFN style packages. These different I/O configurations are: 1. Non Solder masked Defined (NSMD) 2. Solder Masked Defined (SMD) As their titles describe, the NSMD contact pads have the solder mask pulled away from the solderable metallization, while the SMD pads have the solder mask over the edge of the metallization, as shown in Figure 17. With the SMD Pads, the solder mask restricts the flow of solder paste on the top of the metallization which prevents the solder from flowing along the side of the metal pad. This is different from the NSMD configuration where the solder will flow around both the top and the sides of the metallization.
Solder Mask Opening
When dimensionally possible, the solder mask should be located at least a 0.076mm (0.003in) away from the edge of the solderable pad. This spacing is used to compensate for the registration tolerances of the solder mask, as well as to insure that the solder is not inhibited by the mask as it reflows along the sides of the metal pad. The dimensions of the soldermask openings are shown in Figure 18 for a preferred non-soldermask configuration. The dimensions of the PCB's solderable pads should match those of the pads on the package as shown in Figure 19. The 1:1 ratio between the package's pad configuration, and that of the PCB's, is desired for optimal placement accuracy and reliability. Please note that NIS3001 Footprint shows smaller exposed pad openings compared with the recommended PCB layout. Die attach pads on the footprint were divided into smaller exposed pads to help reduce the risk of solder voiding during reflow mounting to the package
12X
0.508
3.810
1.765
12X
0.941
9.992 6.274
4.720
Solder Mask Overlay
Solderable Pad
1.765
6.745
Figure 18. NSMD Openings for PCB Layout
NSMD
SMD
Figure 17. Comparison of NSMD versus SMD pads.
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NIS3001
12X
0.356 0.789
1.689
2X
1.612
0.356
2X
3.658
1.612
12X
3.261 3.439
0.789
3.261
4X 2X
9.840
2.169
R0.380
4X
4.568
2.861
2X
4X
1.612 3.096 NIS3001 Footprint
1.612
6.592
Recommended PCB Pattern for NIS3001 Footprint
Figure 19. Recommended PCB Layout for NIS3001 footprint Thermal/Electrical Vias
Vias are normally placed on the larger die attach pads to improve electrical and thermal performance. If vias are required on the larger die attach pads, our recommendation is to use filled-vias. Filled-vias will help prevent the solder from flowing down into the holes, thereby reducing the solder volume required for the solder joint of this die attach pad. Filled-vias are normally filled with some type of conductive epoxy. If through-hole vias are used, we recommend that the via size be less than or equal to 0.25mm(10 mils). The number of vias placed over the die attach pad is also critical and should not exceed 25% of the total exposed area of the copper pattern. In other words, excessive through-hole vias will allow the solder to flow down into the via and thereby decrease the solder volume needed to have a sufficient solder joint. These vias can be plugged with solder mask material to avoid soldering wicking.
NIS3001 Board Mounting Process
The first metallization consists of an Organic Solderability Preservative coating (OSP) over the copper plated pad. The organic coating assists in reducing oxidation in order to preserve the copper metallization for soldering. The second recommended solderable metallization consists of plated electroless nickel over the copper pad, followed by immersion gold. The thickness of the electroless nickel layer is determined by the allowable internal material stresses and the temperature excursions the board will be subjected to throughout its lifetime. Even though the gold metallization is typically a self-limiting process, the thickness should be at least 0.05 mm thick, and not consist of more than 5% of the overall solder volume. Having excessive gold in the solder joint can create gold embitterment which may affect the reliability of the joint.
Solder Type
The board mounting process is optimized by first defining and controlling the following processes: 1. Creating and maintaining a solderable metallization on the PCB contacts. 2. Choosing the proper solder paste. 3. Screening/stenciling the solder paste onto the PCB. 4. Placing the package onto the PCB. 5. Reflowing the solder paste. 6. Final solder joint inspection. Recommendations for each of these processes are located below.
PCB Solderable metallization
Solder paste such as Cookson Electronics' WS3060 with a Type 3 or smaller sphere size is recommended. The WS3060 has a water-soluble flux for cleaning. Cookson Electronics' PNC0106A can be used if a no-clean flux is preferred.
Solder Screening onto the PCB
There are two common plated solderable metallizations, which are used for PCB surface mount devices. In either case, it is imperative that the plating is uniform, conforming, and free of impurities to insure a consistent solderable system.
Stencil screening the solder onto the PCB board is commonly used in the industry. The recommended stencil thickness to be used is 0.075 mm (0.003 in) and the sidewalls of the stencil openings should be tapered approximately 5 degrees to facilitate the release of the paste when the stencil is removed from the PCB. Note that a 0.127 mm (0.005 in) thick stencil may be used also, but will require smaller stencil openings to reduce the amount of solder applied to equal the amount of solder applied using the 0.075 mm thick stencil. For a typical edge PCB terminal pad, the stencil opening should be the same size as the pad size on the package. However, in cases where the die pad is soldered to the PCB, the stencil opening must be divided into smaller openings
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NIS3001
as shown in Figure 20. Dividing the larger die pads into smaller screen openings reduces the risk of solder voiding and allows the solder joints for the smaller terminal pads to be at the same height as the larger ones.
Package Placement onto the PCB
Temperature (5C)
250 200 183 150 100 50 0 0 100 200
Peak of 225C
Pick and place equipment with the standard tolerance of 0.05 mm or better is recommended. The package will tend to center itself and correct for slight placement errors during the reflow process due to the surface tension of the solder.
12X
Less than 2C/sec
0.356
0.700
6X
33X
1.015
12X
0.789
Figure 21. Typical reflow profile for eutectic tin/lead solder.
Die Attach Pads
4X
1.621
2X
1.000
8X 4X
8X
0.811 0.928 1.856
In general, the temperature of the part should be raised not more than 2C/sec during the initial stages of the reflow profile. The soak zone then occurs when the part is approximately 150C and should last for 30 to 120 seconds. Typically, extending the time in the soak zone will reduce the risk of voiding within the solder. The temperature is then raised and will be above the liquidus of the solder for 30 to 100 seconds depending on the mass of the board. The peak temperature of the profile should be between 205 and 225C for eutectic Sn/Pb solder. If required, removal of the residual solder flux can be completed by using the recommended procedures set forth by the flux manufacturer.
Final Solder Inspection
Figure 20. Solder stencil design illustrating smaller stencil openings over the larger exposed die pads. Solder Reflow
Once the package is placed on the PC board along with the solder paste, a standard surface mount reflow process can be used to mount the part. Figure 21 is an example of a standard reflow profile. The exact profile will be determined, and is available, by the manufacture of the paste since the chemistry and viscosity of the flux matrix will vary. These variations will require small changes in the profile in order to achieve an optimized process.
The inspection of the solder joints is commonly performed with the use of an X-ray inspection system. With this tool, one can locate defects such as shorts between pads, open contacts, voids within the solder as well as any extraneous solder. In addition to searching for defects, the mounted device should be rotated on its side to inspect the sides of the solder joints with an X-ray inspection system. The solder joints should have enough solder volume with the proper stand-off height so that an "Hour Glass" shaped connection is not formed as shown below in Figure 22. "Hour Glass" solder joints are a reliability concern and must be avoided.
Preferred Solder Joint
PCB
Figure 22. Side view of NIS3001 illustrating preferred and undesirable solder joints.
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IIII IIII IIII
IIIIIII I II III II III II
Time Soak Above Zone Liquidus (30 to 120 sec) 300
Time (sec)
400
500
Undesirable "Hour Glass" Solder Joint
II II II
NIS3001
Rework Procedure
Due to the fact that the NIS3001 is a leadless device, the entire package must be removed from the PC board if there is an issue with the solder joints. It is important to minimize the chance of overheating neighboring devices during the removal of the package since the devices are typically in close proximity with each other. Standard SMT rework systems are recommended for this procedure since the airflow and temperature gradients can be carefully controlled. It is also recommend that the PC board be placed in an oven at 125C for 4 to 8 hours prior to heating the parts to remove excess moisture from the packages. In order to control the region, which will be exposed to reflow temperatures, the board should be heated to a 100C by conduction through the backside of the board in the location of the NIS3001 QFN Package. Typically, heating nozzles are then used to increase the temperature locally. Once the NIS3001's solder joints are heated above their liquidus temperature, the package is quickly removed and the pads on the PC board are cleaned. The cleaning of the pads is typically performed with a blade-style conductive tool with a de-soldering braid. A no clean flux is used during this process in order to simplify the procedure. Solder paste is then deposited or screened onto the site in preparation of mounting a new device. Due to the close
proximity of the neighboring packages in most PC board configurations, a miniature stencil for the individual component is typically required. The same stencil design that was originally used to mount the package can be applied to the mini-stencil for redressing the pad. Due to the small pad configurations of the NIS3001, and since the pads are on the underside of the package, a manual pick and place procedure without the aid of magnification is not recommended. A dual image optical system where the underside of the package can be aligned to the PC board should be used instead. Reflowing the component onto the board can be accomplished by either passing the board through the original reflow profile, or by selectively heating the NIS3001 Package with the same process that was used to remove it. The benefit with subjecting the entire board to a second reflow is that the packages will be mounted consistently and by a profile that is already defined. The disadvantage is that all of the other devices mounted with the same solder type will be reflowed for a second time. If subjecting all of the parts to a second is either a concern or unacceptable for a specific application, than the localized reflow option would be the recommended procedure.
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NIS3001
PACKAGE DIMENSIONS
PInPAK 10.5x10.5 QFN CASE 500-01 ISSUE A
4X
D 0.15 C
A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION b APPLIES TO PLATED TERMINAL IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 2.000 2.200 0.000 0.050 1.500 1.700 0.508 REF 10.500 BSC 10.500 BSC 0.306 0.406 3.436 BSC 3.200 BSC 1.969 BSC 2.424 BSC 0.762 BSC 0.762 BSC 0.094 BSC 0.037 BSC 4.114 BSC 0.259 BSC 3.200 BSC 3.289 BSC 1.424 BSC 0.283 BSC 2.188 BSC 3.048 BSC 2.286 BSC 0.154 0.354 0.230 0.430 0.230 0.430 2.936 BSC 1.495 BSC 2.197 BSC 2.361 BSC 2.663 BSC 1.512 1.712 1.589 1.789 3.056 3.256 1.512 1.712 2.821 3.021 3.161 3.361 3.339 3.539 0.689 0.889 2.094 2.244
E
A2
A
0.08 C
A1 A3 e F
C
4X 8X
SEATING PLANE NOTE 3
DETAIL M
P2 L1
0.10
M
CAB
NOTE 3 2X M
P3 N
4X
R
0.10
CAB
L2
e1 C L G G1 G2
2 X R1 2 X R4
e3 e4 H1 H N3 J
DIM A A1 A2 A3 D E b e e1 e2 e3 e4 e5 F F1 F2 G G1 G2 H H1 H2 J K L L1 L2 N N1 N2 N3 N4 P P1 P2 P3 R R1 R2 R3 R4
R2
C L H2 N2
0.10
M
2 X P1 CAB NOTE 3
e2 F1 F2 C L
P NOTE 3 0.10 0.10
M M
CAB CAB
12 X R3 8X
APPLIES TO ALL F AND G DIMENSIONS
L
12 X
B K C L 0.10
N1 e5 N4
0.10
M
CAB
NOTE 3
M
CAB
APPLIES TO ALL H AND N DIMENSIONS
DETAIL M
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NIS3001
PInPAK is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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NIS3001/D

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